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3.1.10.3
Sigma Delta Modulator Over Range Flag (SDOV)
The sigma delta modulator over range flag is set if the sigma delta modulator for either axis becomes saturated. The SDOV
flag is cleared by a read of the DEVSTAT register.
3.1.10.4
Device Initialization Flag (DEVINIT)
The device initialization flag is set during the interval between negation of internal reset and completion of internal device ini-
tialization. DEVINIT is cleared automatically. The device initialization flag is not affected by a read of the DEVSTAT register.
3.1.10.5
SPI MISO Data Mismatch Error Flag (MISOERR)
The MISO data mismatch flag is set when a MISO Data mismatch fault occurs as specified in Section 4.5.2 . The MISOERR
flag is cleared by a read of the DEVSTAT register.
3.1.10.6
Offset Monitor Over Range Flags (OFF_X, OFFSET_Y)
The offset monitor over range flags are set if the acceleration signal of the associated axis reaches the specified offset limit.
The offset monitor over range flags are cleared by a read of the DEVSTAT register.
3.1.10.7
Device Reset Flag (DEVRES)
The device reset flag is set during device initialization following a device reset. The device reset flag is cleared by a read of
the DEVSTAT register.
3.1.11 Count Register (COUNT)
The count register is a read-only register which provides the current value of a free-running 8-bit counter derived from the pri-
mary oscillator. A 10-bit pre-scaler divides the primary oscillator frequency by 1024. Thus, the value in the register increases by
one count every 128 μ s and the counter rolls over every 32.768 ms.
Table 23. Count Register
Location
Bit
Address
$15
Register
COUNT
7
COUNT[7]
6
COUNT[6]
5
COUNT[5]
4
COUNT[4]
3
COUNT[3]
2
COUNT[2]
1
COUNT[1]
0
COUNT[0]
Reset Value
0
0
0
0
0
0
0
0
3.1.12 Offset Correction Value Registers (OFFCORR_X, OFFCORR_Y)
The offset correction value registers are read-only registers which contain the most recent offset correction increment / dec-
rement value from the offset cancellation circuit. The values stored in these registers indicate the amount of offset correction be-
ing applied to the SPI output data. The values have a resolution of 1 LSB.
Table 24. Offset Correction Value Register
Location
Bit
Address
Register
7
6
5
4
3
2
1
0
$16
$17
OFFCORR_X OFFCORR_X[7] OFFCORR_X[6] OFFCORR_X[5] OFFCORR_X[4] OFFCORR_X[3] OFFCORR_X[2] OFFCORR_X[1] OFFCORR_X[0]
OFFCORR_Y OFFCORR_Y[7] OFFCORR_Y[6] OFFCORR_Y[5] OFFCORR_Y[4] OFFCORR_Y[3] OFFCORR_Y[2] OFFCORR_Y[1] OFFCORR_Y[0]
Reset Value
0
0
0
0
0
0
0
0
3.1.13 Reserved Registers (Reserved)
Registers $1C and $1D are reserved. A write to the reserved bits must always be logic ’0’ for normal device operation and
performance.
Table 25. Reserved Registers
Location
Bit
Address
$1C
$1D
Register
Reserved
Reserved
7
Reserved
Reserved
6
Reserved
Reserved
5
Reserved
Reserved
4
Reserved
Reserved
3
Reserved
Reserved
2
Reserved
Reserved
1
Reserved
Reserved
0
Reserved
Reserved
Reset Value
0
0
0
0
0
0
0
0
MMA68xx
Sensors
20
Freescale Semiconductor, Inc.
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